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As a Digital IC Design Engineer you will contribute by developing the next generation of 5G Baseband technology processors. Work with Architects and Verification Engineers to develop complex, high performance and timing critical designs. Be responsible for block level micro architecture design and RTL coding Provide area/power optimization and design trade offs Block and
Posted 3 days ago
Understanding the design requirements and customer specification Pick up and run the defined computer aided design (CAD) tools/flow for the assigned designs Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages) Analyze, debug, and implement DFT features using defined CAD tools/flow Collaborate with global CAD teams on design fl
Posted 3 days ago
In this role as a DFT Verification Engineeryou will develop the functional directed verification for DFT RTL design sub systems. Write a DFT verification test plan using random techniques and coverage analysis, and work with RTL designers to ensureit is complete. Develop tests and tune the environment to achieve coverage goals. Debug simulation failures and work with desi
Posted 3 days ago
Implement modern DFT solutions for leading edge ICs on latest technology nodes. Work with RTL, custom digital/analog, verification, physical implementation, and timingteams duringthis DFT implementation. Set up, run, and debug block level, SOC level as well as full chip ATPG runs Drive successful bring up of test patterns and features post tape out #LI KB1 Requirements Ba
Posted 3 days ago
Marvell Semiconductor, Inc.
- Marlborough, MA / Santa Clara, CA / Morrisville, NC
About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future am
Posted 3 days ago
About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future am
Posted 3 days ago
About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future am
Posted 3 days ago
Responsibilities Develop and support Marvell's block level and partition level construction and signoff flows, incorporating industry standard EDA tools Perform synthesis, PnR, timing analysis, and backend checks on complex logic blocks Develop and implement timing and logic ECOs Interact with the RTL design team to drive design modifications to resolve congestion and tim
Posted 3 days ago
Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete. Develop tests and tune the environment to achieve coverage goals. Debug failures and work with designers to resolve issues. Architecting, developing, and maintaining tools to streamline the design of state of the art multi core SoCs. Transform th
Posted 4 days ago
Marvell Semiconductor, Inc.
- Santa Clara, CA / Austin, TX / Morrisville, NC / 2 more...
As a Physical Design Engineer (Global Timing), you will be part of our Global Timing team and responsible for Running/supporting/maintaining the Global Timing Flow using industry standard EDA tools for designing the next generation Multi Ghz high performance processor SOC chips in leading edge CMOS process technology. Running the Sign off STA flow across all modes and cor
Posted 4 days ago
Marvell Semiconductor, Inc.
- Marlborough, MA / Austin, TX / Santa Clara, CA / 3 more...
Marvell's Processor Business Group (PBG) is looking for an experienced, talented architect to join our architecture team. As an SoC architect, you'll be responsible for Engaging with customers, engineering, and marketing to lead chip architecture of innovative and complex processor based SoCs Architecting new blocks and capabilities Overseeing and coordinating IP evaluati
Posted 4 days ago
Marvell Semiconductor, Inc.
- Burlington, VT / Austin, TX / Santa Clara, CA / 3 more...
Provide technical leadership to a world wide team of engineers who are implementing customer specific designs from RTL hand off through tape out. Lead technical experts across place & route, timing, power, design for test, and packaging domains using design automation tools/flows and scripting languages while employingindustry best practices. Work with stakeholders throug
Posted 4 days ago
Marvell Semiconductor, Inc.
- Burlington, VT / Rochester, MN / Morrisville, NC / 1 more...
Use Cadence Innovus place and route Tempus timing tool (show proficiency in timing closure) Understand Standard Cell library structure using 5,7,14 nm with ability to lead to 3nm. Demonstrate use of High speed clock distribution Have experience with above specified EDA tools to support custom design , simulation, layout. Develop scripts, programs, flows, and methodologies
Posted 5 days ago
Marvell Semiconductor, Inc.
- Burlington, VT / Rochester, MN / Santa Clara, CA / 2 more...
Provide technical leadership to a world wide team of engineers who are implementing customer specific designs from RTL hand off through tape out. Lead technical experts across place & route, timing, power, design for test, and packaging domains using design automation tools/flows and scripting languages while employingindustry best practices. Work with stakeholders throug
Posted 5 days ago
Verify functionality of high performance memory sub system or other subsystems at the unit and/or sub system levels. Develop and execute test plans to verify correctness and performance of the design. Own and debug failures in simulation to root cause problems Closely work with logic designers and architects for test plan development, execution, debug and coverage closure
Posted 5 days ago
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