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In this role, you will work on the verification environment for Marvell Fusion Baseband processor, including testbench architecture, developing reference models, bus functional monitors and drivers to verify the complex hardware powering this product line. Activities may include Writing a verification test plan using random techniques and coverage analysis and working wit
Posted 8 days ago
Physical Design engineer with a focus on full chip and sub hierarchy physical integration Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks through the design flow and making sure all the block level implementations are meeting partition or chip level requirements, such as physical integration and timing require
Posted 8 days ago
Requirements Physical Design engineer with expertise in sub hierarchy integration Have experience integrating and taping out large designs utilizing a digital design environment Work with design teams across various disciplines such as Digital/RTL/Analog to ensure designs converge and integrate in a timely manner. Implement/support designs with multi voltage designs throu
Posted 8 days ago
Strong user of Synopsys PrimeTime (or other equivalent timing tool) including these skills translating design timing requirements into SDC accurate evaluation of PrimeTime timing reports to identify solutions to timing issues extracting relevant timing data from timing runs interactively Strong knowledge on several key static timing analysis concepts which can include cro
Posted 8 days ago
Conduct floor planning, placement, clock insertion, routing, physical checking, and timing closure Utilize problem solving skills to address issues in placement and route, such as congestion Collaborate closely with team members to s trategize on optimization methods to meet power, frequency, and area requirements Implement and debug physical checks such as design rule ch
Posted 11 days ago
As a member of the SoC RTL integration team, our job is to bring Marvell's next generation cloud, networking, security and mobile processors together. Responsibilities include Work with Architects, IP RTL development teams, Verification teams and Physical Design teams to integrate complex, high performance IP into a cohesive product Be responsible for integration level RT
Posted 11 days ago
Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes. Assist in planning and designating project resources, monitor progress, and keep stakeholders informed the entire way. Partner with other ASIC design teams to ensure project success. Possibility of being management interface to A
Posted 11 days ago
Developing, enhancing, and supporting Marvell processor business unit's global timing and noise sign off flow, incorporating industry standard EDA tools Ownership of timing closure for a portion of a chip or for the full chip Development and implementation of timing and logic ECO's using automated and manual approaches Interacting with the RTL design team to understand ti
Posted 21 days ago
Responsibilities Develop understanding the SOC design requirements and specification. Develop understanding the computer aided design (CAD) tools/flow defined for ASICs. Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages). Analyze, debug, and implement fixes for reported timing violations (setup, hold, slew, and capacitance)
Posted 22 days ago
Job Responsibilities Understanding the design requirements and customer specification Pick up and run the defined computer aided design (CAD) tools/flow for the assigned designs Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages) Analyze, debug, and implement DFT features using defined CAD tools/flow Collaborate with global C
Posted 1 month ago
Marvell Semiconductor, Inc.
- Marlborough, MA / Morrisville, NC
Develop and support Marvell's block level and partition level construction and signoff flows, incorporating industry standard EDA tools Perform synthesis, PnR, timing analysis, and backend checks on complex logic blocks Develop and implement timing and logic ECOs Interact with the RTL design team to drive design modifications to resolve congestion and timing issues Work w
Posted 1 month ago
As a Digital IC Design Engineer you will contribute by developing the next generation of cloud, networking, and security processors. Work with Architects and Verification Engineers to develop complex, high performance and timing critical designs. Be responsible for block level micro architecture design and RTL coding Provide area/power optimization and design trade offs B
Posted 1 month ago
Marvell Semiconductor, Inc.
- Marlborough, MA / Morrisville, NC
As a Digital IC Design Engineer you will contribute by developing the next generation of cloud, networking, and security processors. Work with Architects and Verification Engineers to develop complex, high performance and timing critical designs. Be responsible for block level micro architecture design and RTL coding Provide area/power optimization and design trade offs B
Posted 1 month ago
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