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Understanding the design requirements and customer specification Pick up and run the defined computer aided design (CAD) tools/flow for the assigned designs Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages) Analyze, debug, and implement DFT features using defined CAD tools/flow Collaborate with global CAD teams on design fl
Posted 11 days ago
Marvell Semiconductor, Inc.
- Marlborough, MA / Morrisville, NC
One or more of the following Maintain, enhance, and support Marvell's place and route, timing and/or integration flows incorporating industry standard EDA tools Perform synthesis, floor planning, place and route, timing analysis, and/or closure on complex logic blocks. Develop and implement timing closure and logical ECO's. Interface with the RTL design team to drive desi
Posted 11 days ago
Job Duties Perform RTL coding Perform functional verification of design on block and system level. Support synthesis and timing closure. Provide design documentation, description and information to application engineers, field application engineers, test engineers, production engineers and customers. Job Requirement You must be familiar with Digital IC design methodologie
Posted 11 days ago
Analyze architectures and designs to create comprehensive test plans and strategies Contribute to the development of verification environments, including reference models, sequences, agents, and scoreboards. Develop tests/testing strategies to achieve coverage goals. Debug failures and work with designers to resolve issues. Work and communicate effectively with global tea
Posted 11 days ago
Assist ASIC BU and customers on IP selections accordingly to product requirements. Assist customers and design teams on design integration of the IPs, logically and physically. Conduct IP usage reviews and design sign of with customers and design teams. Provide assistance on hardware test and hardware bring up debug. Lead lesson learn with Design Center teams and IP devel
Posted 11 days ago
Responsibilities Develop and support Marvell's block level and partition level construction and signoff flows, incorporating industry standard EDA tools Perform synthesis, PnR, timing analysis, and backend checks on complex logic blocks Develop and implement timing and logic ECOs Interact with the RTL design team to drive design modifications to resolve congestion and tim
Posted 11 days ago
Developing, enhancing, and supporting Marvell processor business unit's global timing and noise sign off flow, incorporating industry standard EDA tools Ownership of timing closure for a portion of a chip or for the full chip Development and implementation of timing and logic ECO's using automated and manual approaches Interacting with the RTL design team to understand ti
Posted 11 days ago
Strong user of Synopsys PrimeTime (or other equivalent timing tool) including these skills translating design timing requirements into SDC accurate evaluation of PrimeTime timing reports to identify solutions to timing issues extracting relevant timing data from timing runs interactively Strong knowledge on several key static timing analysis concepts which can include cro
Posted 11 days ago
Verify functionality of high performance memory sub system or other subsystems at the unit and/or sub system levels. Develop and execute test plans to verify correctness and performance of the design. Own and debug failures in simulation to root cause problems Closely work with logic designers and architects for test plan development, execution, debug and coverage closure
Posted 11 days ago
Implement modern DFT solutions for leading edge ICs on latest technology nodes. Work with RTL, custom digital/analog, verification, physical implementation, and timingteams duringthis DFT implementation. Set up, run, and debug block level, SOC level as well as full chip ATPG runs Drive successful bring up of test patterns and features post tape out #LI KB1 Requirements Ba
Posted 11 days ago
Marvell Semiconductor, Inc.
- Marlborough, MA / Santa Clara, CA / Morrisville, NC / 3 more...
Marvell's Processor Business Group (PBG) is looking for an experienced, talented architect to join our architecture team. As an SoC architect, you'll be responsible for Engaging with customers, engineering, and marketing to lead chip architecture of innovative and complex processor based SoCs Architecting new blocks and capabilities Overseeing and coordinating IP evaluati
Posted 11 days ago
In this role as a DFT Verification Engineeryou will develop the functional directed verification for DFT RTL design sub systems. Write a DFT verification test plan using random techniques and coverage analysis, and work with RTL designers to ensureit is complete. Develop tests and tune the environment to achieve coverage goals. Debug simulation failures and work with desi
Posted 11 days ago
Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete. Develop tests and tune the environment to achieve coverage goals. Debug failures and work with designers to resolve issues. Architecting, developing, and maintaining tools to streamline the design of state of the art multi core SoCs. Transform th
Posted 11 days ago
Manage overall ASIC product family profit & loss. Manage product costs to meet internal and externalneeds Drive annual reviews of product plan vs actualperformance Review/Input product cost into annual budgets Review key production, quality, cost, and EOL issues with BU and Operations leadershipteam s Ensure customer satisfaction, driving customer loyalty Manage overall p
Posted 11 days ago
As a Digital IC Design Engineer you will contribute by developing the next generation of 5G Baseband technology processors. Work with Architects and Verification Engineers to develop complex, high performance and timing critical designs. Be responsible for block level micro architecture design and RTL coding Provide area/power optimization and design trade offs Block and
Posted 11 days ago
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