At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
The OpportunityThe Central Engineering ASIC Design Services Team within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, enterprise, and automotive applications. As a manager within the ASIC team, you will have the opportunity to lead an experienced team and growing team of physical design, static timing analysis (STA) and design for test (DFT) engineers. You will also have the opportunity to interact with customers and the worldwide team to develop solutions to meet our customer's needs.
Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
* Assist in planning and designating project resources, monitor progress, and keep stakeholders informed the entire way.
* Partner with other ASIC design teams to ensure project success.
* Possibility of being management interface to ASIC customers.
* Lead recruiting efforts at local universities and hiring of experienced engineers.
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
* Must have a background in ASIC or SOC development
* Physical design knowledge, from netlist handoff to GDS tape-out including floor planning, place and route, clock tree synthesis, timing closure and physical verification.
* Must be able to handle a wide variety of projects and technical challenges.
* Diligent, detail-oriented, and able to handle assignments with minimal supervision.
* The successful candidate will have excellent written and oral communications skills, and ability to collaborate and be effective in fast-paced environment.
* Self-driven individual and with ability to partner with world-wide team.
* Proven track record of team mentorship for high performance
* Technical leadership of ASIC or SOC Netlist to GDS tape-out
* Experience as either top-level physical design lead, STA chip Lead or chip DFT lead
* Project management experience of ASIC or SOC.
* Experience working with a distributed team#LI-JS22The Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at or 408-222-3604.