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About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Custom Compute and Storage Team (CCS) within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, enterprise, automotive, and storage applications. As a manager within this team, you will have the opportunity to lead an experienced and growing team of physical design, static timing analysis (STA) and Power Integrity engineers. You will also have the opportunity to interact with customers and the worldwide team to develop solutions to meet our customer's needs.What You Can Expect
Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
Assist in planning and designating project resources, monitor progress, and keep stakeholders informed the entire way.
Partner with other CCS design teams to ensure project success.
Possibility of management interface to CCS customers.
Lead recruiting efforts at local universities and hiring of experienced engineers.
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Must have a background in ASIC or SOC development Physical design knowledge, from netlist handoff to GDS tape-out including floor planning, place and route, clock tree synthesis, timing closure and physical verification.
Must be able to handle a wide variety of projects and technical challenges. Diligent, detail-oriented, and able to handle assignments with minimal supervision.
Must have excellent written and oral communications skills, and ability to collaborate and be effective in fast-paced environment. Self-driven individual and with ability to partner with world-wide team.
Preferred Qualifications:
Proven track record of team mentorship for high performance Technical leadership of ASIC or SOC Netlist to GDS tape-out
Experience as either top-level physical design lead or STA chip Lead Project management experience of ASIC or SOC.
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Expected Base Pay Range (USD)
151,900 - 224,780, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .